/*
* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: BSD-3-Clause
*/

#ifndef BSP_CLOCK_CFG_H_
#define BSP_CLOCK_CFG_H_
#define BSP_CFG_CLOCKS_SECURE (0)
#define BSP_CFG_CLOCKS_OVERRIDE (0)
#define BSP_CFG_CLOCK_OSCCLK_HZ (24000000) /* OSC 24000000Hz */
#define BSP_CFG_CLOCK_PLLCM33CLK_HZ (1600000000) /* PLLCM33 1600000000Hz */
#define BSP_CFG_CDDIV0_DIVCTL0_DIV (BSP_CLOCKS_PLLCM33_CST400_DIV_2) /* Div /2 */
#define BSP_CFG_CLOCK_ATCLK_HZ (400000000) /* ATCLK 400000000Hz */
#define BSP_CFG_CDDIV0_DIVCTL1_DIV (BSP_CLOCKS_PLLCM33_DIV_2) /* Div /2 */
#define BSP_CFG_CLOCK_I7CLK_HZ (200000000) /* I7CLK 200000000Hz */
#define BSP_CFG_CLOCK_P0CLK_HZ (100000000) /* P0CLK 100000000Hz */
#define BSP_CFG_CLOCK_P1CLK_HZ (100000000) /* P1CLK 100000000Hz */
#define BSP_CFG_CLOCK_P2CLK_HZ (50000000) /* P2CLK 50000000Hz */
#define BSP_CFG_CSDIV1_DIVCTL0_DIV (BSP_CLOCKS_PLLCM33_ADC_PCLK_DIV_8) /* Div /8 */
#define BSP_CFG_CSDIV1_DIVCTL1_DIV (BSP_CLOCKS_PLLCM33_ADC_ADCLK_DIV_2) /* Div /2 */
#define BSP_CFG_CLOCK_ADCCLK_HZ (50000000) /* ADCCLK 50000000Hz */
#define BSP_CFG_SSEL1_SELCTL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_SSEL1_SELCTL2_CDIV3_CLK533_PLLCM33_FIX) /* Sel: 533MHz */
#define BSP_CFG_SSEL1_SELCTL3_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_SSEL1_SELCTL3_SMUX2_XSPI_CLK0) /* Sel: SMUX2_XSPI_CLK0 */
#define BSP_CFG_CSDIV0_DIVCTL3_DIV (BSP_CLOCKS_PLLCM33_XSPI_DIV_2) /* Div /2 */
#define BSP_CFG_CLOCK_SPI0CLK_HZ (266666666) /* SPI0CLK 266666666Hz */
#define BSP_CFG_CLOCK_SPI1CLK_HZ (133333333) /* SPI1CLK 133333333Hz */
#define BSP_CFG_CLOCK_PLLCLNCLK_HZ (1600000000) /* PLLCLN 1600000000Hz */
#define BSP_CFG_CLOCK_SDCLK_HZ (800000000) /* SDCLK 800000000Hz */
#define BSP_CFG_CLOCK_P3CLK_HZ (400000000) /* P3CLK 400000000Hz */
#define BSP_CFG_CLOCK_P4CLK_HZ (200000000) /* P4CLK 200000000Hz */
#define BSP_CFG_CLOCK_P5CLK_HZ (100000000) /* P5CLK 100000000Hz */
#define BSP_CFG_CLOCK_CANCLK_HZ (80000000) /* CANCLK 80000000Hz */
#define BSP_CFG_CLOCK_P6CLK_HZ (50000000) /* P6CLK 50000000Hz */
#define BSP_CFG_CLOCK_PLLDTYCLK_HZ (1600000000) /* PLLDTY 1600000000Hz */
#define BSP_CFG_CDDIV2_DIVCTL1_DIV (BSP_CLOCKS_PLLDTY_CR8_DIV_2) /* Div /2 */
#define BSP_CFG_CLOCK_I6CLK_HZ (800000000) /* I6CLK 800000000Hz */
#define BSP_CFG_CDDIV0_DIVCTL2_DIV (BSP_CLOCKS_PLLDTY_ACPU_DIV_2) /* Div /2 */
#define BSP_CFG_CLOCK_P7CLK_HZ (400000000) /* P7CLK 400000000Hz */
#define BSP_CFG_CLOCK_P8CLK_HZ (200000000) /* P8CLK 200000000Hz */
#define BSP_CFG_CLOCK_P9CLK_HZ (100000000) /* P9CLK 100000000Hz */
#define BSP_CFG_CLOCK_P10CLK_HZ (200000000) /* P10CLK 200000000Hz */
#define BSP_CFG_CLOCK_ZTCLK_HZ (100000000) /* ZTCLK 100000000Hz */
#define BSP_CFG_CDDIV3_DIVCTL2_DIV (BSP_CLOCKS_PLLDTY_RCPU_DIV_2) /* Div /2 */
#define BSP_CFG_CLOCK_P11CLK_HZ (200000000) /* P11CLK 200000000Hz */
#define BSP_CFG_CDDIV2_DIVCTL2_DIV (BSP_CLOCKS_PLLDTY_DRP_DIV_2) /* Div /2 */
#define BSP_CFG_CLOCK_P12CLK_HZ (400000000) /* P12CLK 400000000Hz */
#define BSP_CFG_CLOCK_PLLCA55CLK_HZ (1800000000) /* PLLCA55 1800000000Hz */
#define BSP_CFG_CDDIV1_DIVCTL0_DIV (BSP_CLOCKS_CLK1800_PLLCA55_CA55_0_DIV_1) /* Div /1 */
#define BSP_CFG_CLOCK_I0CLK_HZ (1800000000) /* I0CLK 1800000000Hz */
#define BSP_CFG_CDDIV1_DIVCTL1_DIV (BSP_CLOCKS_CLK1800_PLLCA55_CA55_1_DIV_1) /* Div /1 */
#define BSP_CFG_CLOCK_I1CLK_HZ (1800000000) /* I1CLK 1800000000Hz */
#define BSP_CFG_CDDIV1_DIVCTL2_DIV (BSP_CLOCKS_CLK1800_PLLCA55_CA55_2_DIV_1) /* Div /1 */
#define BSP_CFG_CLOCK_I2CLK_HZ (1800000000) /* I2CLK 1800000000Hz */
#define BSP_CFG_CDDIV1_DIVCTL3_DIV (BSP_CLOCKS_CLK1800_PLLCA55_CA55_3_DIV_1) /* Div /1 */
#define BSP_CFG_CLOCK_I3CLK_HZ (1800000000) /* I3CLK 1800000000Hz */
#define BSP_CFG_CDDIV2_DIVCTL0_DIV (BSP_CLOCKS_PLLCA55PERI_DIV_2) /* Div /2 */
#define BSP_CFG_CLOCK_I4CLK_HZ (450000000) /* I4CLK 450000000Hz */
#define BSP_CFG_CLOCK_PLLDRPCLK_HZ (1260000000) /* PLLDRP 1260000000Hz */
#define BSP_CFG_SSEL0_SELCTL1_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_SSEL0_SELCTL1_PLLDRP) /* Sel: PLLDRP */
#define BSP_CFG_SSEL0_SELCTL0_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_SSEL0_SELCTL0_SMUX2_CA55_SCLK0) /* Sel: SMUX2_CA55_SCLK0 */
#define BSP_CFG_CDDIV0_DIVCTL3_DIV (BSP_CLOCKS_PLLCA55_SCLK_DIV_1) /* Div /1 */
#define BSP_CFG_CLOCK_I5CLK_HZ (1260000000) /* I5CLK 1260000000Hz */
#define BSP_CFG_CLOCK_PLLVDOCLK_HZ (1260000000) /* PLLVDO 1260000000Hz */
#define BSP_CFG_CDDIV3_DIVCTL3_DIV (BSP_CLOCKS_PLLVDO_CRU0_DIV_2) /* Div /2 */
#define BSP_CFG_CLOCK_M0CLK_HZ (630000000) /* M0CLK 630000000Hz */
#define BSP_CFG_CDDIV4_DIVCTL0_DIV (BSP_CLOCKS_PLLVDO_CRU1_DIV_2) /* Div /2 */
#define BSP_CFG_CLOCK_M1CLK_HZ (630000000) /* M1CLK 630000000Hz */
#define BSP_CFG_CDDIV4_DIVCTL1_DIV (BSP_CLOCKS_PLLVDO_CRU2_DIV_2) /* Div /2 */
#define BSP_CFG_CLOCK_M2CLK_HZ (630000000) /* M2CLK 630000000Hz */
#define BSP_CFG_CDDIV4_DIVCTL2_DIV (BSP_CLOCKS_PLLVDO_CRU3_DIV_2) /* Div /2 */
#define BSP_CFG_CLOCK_M3CLK_HZ (630000000) /* M3CLK 630000000Hz */
#define BSP_CFG_CDDIV2_DIVCTL3_DIV (BSP_CLOCKS_PLLVDO_ISP_DIV_2) /* Div /2 */
#define BSP_CFG_CLOCK_ISPCLK_HZ (630000000) /* ISPCLK 630000000Hz */
#define BSP_CFG_CDDIV3_DIVCTL0_DIV (BSP_CLOCKS_PLLVDO_ISU_DIV_2) /* Div /2 */
#define BSP_CFG_CLOCK_ISUCLK_HZ (630000000) /* ISUCLK 630000000Hz */
#define BSP_CFG_CLOCK_PLLETHCLK_HZ (1000000000) /* PLLETH 1000000000Hz */
#define BSP_CFG_CSDIV0_DIVCTL0_DIV (BSP_CLOCKS_PLLETH_GBE0_DIV_2) /* Div /2 */
#define BSP_CFG_SSEL0_SELCTL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_SSEL0_SELCTL2_CSDIV_PLLETH_GBE0) /* Sel: PLLETH_GBE0_GEAR */
#define BSP_CFG_CLOCK_ETHTX0CLK_HZ (125000000) /* ETHTX0CLK 125000000Hz */
#define BSP_CFG_CLOCK_ET0_TXC_TXCLK_HZ (125000000) /* ET0_TXC_TXCLK 125000000Hz */
#define BSP_CFG_SSEL0_SELCTL3_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_SSEL0_SELCTL3_ET0_RXC_RX_CLK) /* Sel: ET0_RXC_RXCLK */
#define BSP_CFG_CLOCK_ETHRX0CLK_HZ (125000000) /* ETHRX0CLK 125000000Hz */
#define BSP_CFG_CLOCK_ET0_RXC_RXCLK_HZ (125000000) /* ET0_RXC_RXCLK 125000000Hz */
#define BSP_CFG_CSDIV0_DIVCTL1_DIV (BSP_CLOCKS_PLLETH_GBE1_DIV_2) /* Div /2 */
#define BSP_CFG_SSEL1_SELCTL0_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_SSEL1_SELCTL0_CSDIV_PLLETH_GBE1) /* Sel: PLLETH_GBE1_GEAR */
#define BSP_CFG_CLOCK_ETHTX1CLK_HZ (125000000) /* ETHTX1CLK 125000000Hz */
#define BSP_CFG_CLOCK_ET1_TXC_TXCLK_HZ (125000000) /* ET1_TXC_TXCLK 125000000Hz */
#define BSP_CFG_SSEL1_SELCTL1_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_SSEL1_SELCTL1_ET1_RXC_RX_CLK) /* Sel: ET1_RXC_RXCLK */
#define BSP_CFG_CLOCK_ETHRX1CLK_HZ (125000000) /* ETHRX1CLK 125000000Hz */
#define BSP_CFG_CLOCK_ET1_RXC_RXCLK_HZ (125000000) /* ET1_RXC_RXCLK 125000000Hz */
#define BSP_CFG_CLOCK_HPCLK_HZ (125000000) /* HPCLK 125000000Hz */
#define BSP_CFG_CSDIV0_DIVCTL2_DIV (BSP_CLOCKS_PLLETH_LPCLK_DIV_16) /* Div /16 */
#define BSP_CFG_CLOCK_LPCLK_HZ (15625000) /* LPCLK 15625000Hz */
#define BSP_CFG_CLOCK_PLLDSICLK_HZ (297000000) /* PLLDSI 297000000Hz */
#define BSP_CFG_CSDIV1_DIVCTL2_DIV (BSP_CLOCKS_PLLDSI_DIV_2) /* Div /2 */
#define BSP_CFG_CLOCK_M4CLK_HZ (148500000) /* M4CLK 148500000Hz */
#define BSP_CFG_CLOCK_PLLGPUCLK_HZ (1260000000) /* PLLGPU 1260000000Hz */
#define BSP_CFG_CDDIV3_DIVCTL1_DIV (BSP_CLOCKS_PLLGPU_DIV_2) /* Div /2 */
#define BSP_CFG_CLOCK_GPUCLK_HZ (630000000) /* GPUCLK 630000000Hz */
#define BSP_CFG_CLOCK_PLLDDR0CLK_HZ (800000000) /* PLLDDR0 800000000Hz */
#define BSP_CFG_CLOCK_PLLDDR1CLK_HZ (800000000) /* PLLDDR1 800000000Hz */
#define BSP_CFG_CLOCK_OSC2CLK_HZ (4800000) /* OSC2CLK 4800000Hz */
#endif /* BSP_CLOCK_CFG_H_ */
